1982 Finish Master Course of Information Engineering, Kyoto Univeristy
1985 Quit Dr. Course of Egineering Course, Kyoto University
1989 Obtained Dr. of Engineering degree at Kyoto University
for a thesis entitled "Logic Simulation Based on Regular Expressions".

Career
1985 Assistant Professor, Kobe Univ.
1989-1990 Visiting Scientist of Carnegie Mellon University
1993 Associate Professor, NAIST
2002 Professor, Waseda University

Academic Committee
2005−2007 Editor of Transactions of Information Processing Society of Japan
2005−2006 Chair of Special Interest Group of VLSI Design Methodology in IEICE (Institute of Electronics, Information and Communication Engineers, Japan)
2005 Guest Editor of IEICE (Institute of Electronics, Information and Communication Engineers, Japan) Transaction, Special Issue "VLSI Design and CAD Algorithms"
*Award Asia and South Pacific Design Automation Conference, University LSI Design Special Feature Award (2000)

In our laboratory, we have been studying the design methodologies of LSI's (Large Scale Integrated Circuits), which are the basis of almost all electronic systems. We focus on the methodologies for designing high performance LSI's with short design time and without design bugs. They include high (abstraction) level design methodologies, the verification methodologies to show the correctness of the LSI design, and the hardware algorithm design for such methodologies. In the LSI design, more than 60% of the design time is consumed by the verification, so we are developing the verifiable design methodologies with designing application LSI's.